www.gusucode.com > dsp 案例源码程序 matlab代码 > dsp/HDLFIRRateConversionBlock6PortExample.m

    %% Control Data Rate Using the Ready and Request Ports 
% Convert a signal from 40 MHz to 100 MHz using the FIR Rate Converter HDL 
% Optimized block. Uses the optional |request| input signal and |ready| 
% output signal to control the data rate.
%
% * To represent a system clock rate of 200MHz, the model connects a repeating 
% true-false signal to the |request| port. This configuration generates output 
% samples at 100 MHz, i.e. every second time step. Alternatively, you can connect 
% this port to the |ready| port of a downstream block. 
% * When the block can accept a new input sample on the next time step, it 
% sets the |ready| output signal to |true|. The model connects this signal
% to a waveform source that generates one sample at a time. 

%% Open the Model
sys = 'FIRRateConversionHDL_interpReadyRequest';
load_system(sys)
set_param(sys,'SimulationCommand','Update')
open_system(sys)

%% Configure the Model
% Define the data rate parameters in the |InitFcn| callback. 
%
% <<../FIRRCHDL_interp_InitFcn.png>>
%
% Configure the FIR Rate Conversion HDL Optimized block. Use an interpolation 
% factor of 5 and a decimation factor of 2. Use the |firmpm| function to design 
% an equiripple FIR filter. Select both check boxes to enable the |ready| 
% and |request| ports. % In the *Data Types* group, set the *Coefficients* 
% data type to |fixdt(1,16,15)| to 
% accommodate your filter design. 

%% Run the Model and Display Results
% Run the model. Use the *Logic Analyzer* to view the input and output signals
% of the block. The blue icon in the model indicates streamed signals. 
% Launch the Logic Analyzer from the model's toolbar.
% 
% <<../analyzebuttondownarrow.png>>
%
% In the *Logic Analyzer*, note the pattern of |request| and the resulting 
% |validOut| signal, and the pattern of |ready| and the resulting |validIn| 
% signal. 
%
% <<../FIRRCHDL_interp_LASignalsZoomedIn.png>>

%% Generate HDL Code
% To generate HDL code from the FIR Rate Converter HDL Optimized block,  
% right-click the block and select *Create Subsystem from Selection*. Then 
% right-click the subsystem and select *HDL Code* > *Generate HDL Code for Susbsystem*.