www.gusucode.com > ecoder 案例源码程序 matlab代码 > ecoder/UserspecifiedbufferreuseExample.m
%% Specify Buffer Reuse for Multiple Signals in a Path % Use a Simulink signal object to specify buffer reuse for multiple % signals in a path. The path can include a pair of root inport and % outport signals. This optimization reduces ROM and RAM consumption % because there are less global variables and data copies in the generated % code. Code execution speed also increases. % %% Example Model % The model <matlab: rtwdemo_reusable_csc_scheduling> contains the nonreusable % subsystems |LPSub| and |HPSub| and the reusable subsystems |MaxSub1| and % |MaxSub2|. % model ='rtwdemo_reusable_csc_scheduling'; open_system(model); set_param(model,'IncludeMdlTerminateFcn', 'on'); %% Specify a Simulink Signal Object for Reuse % % # Open the base workspace. The Simulink signal object |reuse| is for % specifying which buffers to reuse in the generated code. To use % a Simulink signal object for buffer reuse, the object must have a *Storage class* % of |Reusable (Custom)|. % # Right-click one of the signal lines that has the signal name |reuse|. % # Specify a name for the *Signal name* parameter and select the checkbox *Signal name* % *must resolve to Simulink signal object*. % %% Generate Code % Build the model. %% currentDir = pwd; [~,cgDir] = rtwdemodir(); rtwbuild(model); %% % The |rtwdemo_reusable_csc_rescheduling.c| file contains this global % variable for buffer reuse. %% % |/* Definition for custom storage class: Reusable */| %% % |real_T reuse[256];| %% % The |rtwdemo_reusable_csc_scheduling_step| function contains this code. cfile = fullfile(cgDir,'rtwdemo_reusable_csc_scheduling_ert_rtw','rtwdemo_reusable_csc_scheduling.c'); rtwdemodbtype(cfile,'/* Model step function', '/* Model initialize function ', 1, 0); %% % All five functions in the |rtwdemo_reusable_csc_scheduling_step| function % use the global variable |reuse|. In the functions |MaxSub1| , |MaxSub2| , and % |f|, |reuse| is a function argument. In the functions |LPSub| and |HPSub|, |reuse| % is in the function body. %% bdclose(model) rtwdemoclean; cd(currentDir) displayEndOfDemoMessage(mfilename) %% Buffer Reuse for Unit Delay and Delay Blocks % To reuse the signal of a Unit Delay or Delay block % % # Use the same reusable custom storage class specification for a pair of % input and state arguments or a pair of output and state arguments of a % Unit Delay block or a Delay block. % # Open the Unit Delay or Delay block parameters dialog box. % # On the *State Attributes* tab, set the *State name* parameter to the name of the % |Simulink.signal| that you want to reuse. % # On the *State Attributes* tab, select *Signal name must resolve to Simulink* % *signal object*. % # On the *Main* tab, the *Delay length* parameter must have a value of |1|. % The *Initial condition > Source parameter* must be set to |Dialog|. % %% Limitations for Root Inport and Outport Signals % The following limitations apply to a model in which you specify buffer % reuse for a pair of root inport and outport signals. % % * The output ports cannot be conditional. % * If the code generator cannot reuse the same buffer in a top model, % the generated code contains additional buffers. If the same model is a reference model, the % code generator reports an error. To resolve the error, remove the % Simulink.signal specification from the signal that connects to the outport port. % * When you run an executable produced by code generation, and you reuse a % pair of root inport and outport signals, when the root input value is zero, the root output value must also be zero. If the % output value is nonzero and you reuse the signals, then the results from % the simulation can differ from the results produced by the executable. % %% Limitations for the Model % The following limitations apply to a model in which you specify buffer % reuse for signals. % % * Signals that you specify for reuse must have the same data types and sampling rates. % * For user-specified buffer reuse, blocks that modify a signal % specified for reuse must execute before blocks that use the original % signal value. Sometimes the code generator has to change the block % operation order so that buffer reuse can occur. For models in which the % code generator is unable to reorder block operations, buffer reuse does % not occur. % * For models in which the code generator reorders block operations so that % |Simulink.Signal| reuse can occur, you can observe the difference in the % sorted order. In the model window, select *Display > Blocks > Sorted Execution % Order*. To display the sorted execution order during simulation, select % *Simulation > Update Diagram*. To display the execution order in the % generated code, select *Code > C/C++ Code > Build Model*.