标题:免缩放因子CORDIC算法改进及FPGA实现
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上传时间: 2017-07-08 21:12:18
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20170708091230906
内容:
本设计对免缩放因子CORDIC算法进一步改进,改进包括进一步减少迭代次数和减少双步CORDIC算法中区间折叠模块输出调整方式。将改进后的算法与免缩放因子单步算法和免缩放因子双步算法相结合,给出一种正余弦波形产生的架构。用Verilog编写RTL级实现改进后的架构代码,仿真输出与Matlab数据对比,其中正余弦误差都集中在2%以下。在Altera EP2C70F89C6芯片上做FPGA验证,时钟频率可达1000MHz。 This design further improves the anti-scaling factor CORDIC algorithm, including further reducing the number of iterations and reducing the output adjustment of the interval folding module in the two-step CORDIC algorithm. The improved algorithm is combined with the anti - scaling factor single - step algorithm and the anti - scaling factor two - step algorithm to give a structure of sine and cosine waveforms. Verilog prepared by the RTL level to achieve improved architecture code, simulation output and Matlab data comparison, where the sine and cosine errors are concentrated in less than 2%. In the Altera EP2C70F89C6 chip FPGA verification, the clock frequency up to 1000MHz.
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